000 01150nam a22001697a 4500
999 _c35464
_d35464
003 OSt
020 _a9789380501550
082 _a621.395 WAN-V
100 _aWang, Laung-Terng
245 _aVLSI Test Principles and Architecture Design for Textability
260 _aNew York
_bElsevier
_c2006
300 _a777p.
500 _aChapter 1 – Introduction Chapter 2 – Design for Testability Chapter 3 – Logic and Fault Simulation Chapter 4 – Test Generation Chapter 5 – Logic Built-In Self-Test Chapter 6 – Test Compression Chapter 7 – Logic Diagnosis Chapter 8 – Memory Testing and Built-In Self-Test Chapter 9 – Memory Diagnosis and Built-In Self-Repair Chapter 10 – Boundary Scan and Core-Based Testing Chapter 11 – Analog and Mixed-Signal Testing Chapter 12 – Test Technology Trends in the Nanometer Age Details
856 _uhttps://books.google.co.in/books?id=P1ea4znZhGsC&printsec=frontcover&dq=vlsi+test+principles+and+architectures+by+wang&hl=en&sa=X&ved=0ahUKEwjDyqGL27DhAhUHS48KHfFDBfkQ6AEIKzAA#v=onepage&q=vlsi%20test%20principles%20and%20architectures%20by%20wang&f=false
901 _a23314
942 _2ddc
_cBK