TY  - BOOK
AU  - Palnitkar, Samir
AU  - Samir Palnitkar
TI  - Verilog HDL : A Guide to Digital Design
SN  - 9788177589184
U1  - 9788177589184 
PY  - 2013///
PB  - Pearson
N1  - BASIC VERILOG TOPICS.
Overview of Digital Design with Verilog HDL.
Hierarchical Modeling Concepts.
Basic Concepts.
Modules and Ports.
Gate-Level Modeling.
Dataflow Modeling.
Behavioral Modeling.
Tasks and Functions.
Useful Modeling Techniques.
ADVANCED VERILOG TOPICS.
Timing and Delays.
Switch Level Modeling.
User-Defined Primitives.
Programming Language Interface.
Logic Synthesis with Verilog HDL.
Advanced Verification Techniques
UR  - https://books.google.co.in/books?id=fCSIpgsqkhkC&printsec=frontcover&dq=verilog+hdl+by+palnitkar&hl=en&sa=X&ved=0ahUKEwiQjrXpoLbhAhWkW3wKHQruDuUQ6AEIKDAA#v=onepage&q=verilog%20hdl%20by%20palnitkar&f=false
ER  -