Digital Design
Mano, M. Morris
Digital Design - 6th - Chennai Pearson 2018 - 765p.
Table of Content
Chapter 1: Digital Systems and Binary Numbers
Chapter 2: Boolean Algebra and Logic Gates
Chapter 3: Gate-Level Minimization
Chapter 4: Combinational Logic
Chapter 5: Synchronous Sequential Logic
Chapter 6: Registers and Counters
Chapter 7: Memory and Programmable Logic
Chapter 8: Design at the Register Transfer Level
Chapter 9: Asynchronous Sequential Logic
Chapter 10: Digital Integrated Circuits
Chapter 11: Standard Graphic Symbols
Online - Chapter ??12: Laboratory Experiments with Standard ICs and FPGAs"
Salient Features
1. A parallel, but integrated, treatment of Verilog and VHDL, the main hardware description languages used in industry today makes the core text available to a wider audience of students and instructor backgrounds.
2. Examples are presented in both Verilog and VHDL.
3. An introduction to SystemVerilog has been added to the text.
4. Problems at the end of the chapters have been revised, and are stated in terms of a generic HDL, enabling the instructor to choose the language being used by the students.
9789353062019
621.395 MAN-D
Digital Design - 6th - Chennai Pearson 2018 - 765p.
Table of Content
Chapter 1: Digital Systems and Binary Numbers
Chapter 2: Boolean Algebra and Logic Gates
Chapter 3: Gate-Level Minimization
Chapter 4: Combinational Logic
Chapter 5: Synchronous Sequential Logic
Chapter 6: Registers and Counters
Chapter 7: Memory and Programmable Logic
Chapter 8: Design at the Register Transfer Level
Chapter 9: Asynchronous Sequential Logic
Chapter 10: Digital Integrated Circuits
Chapter 11: Standard Graphic Symbols
Online - Chapter ??12: Laboratory Experiments with Standard ICs and FPGAs"
Salient Features
1. A parallel, but integrated, treatment of Verilog and VHDL, the main hardware description languages used in industry today makes the core text available to a wider audience of students and instructor backgrounds.
2. Examples are presented in both Verilog and VHDL.
3. An introduction to SystemVerilog has been added to the text.
4. Problems at the end of the chapters have been revised, and are stated in terms of a generic HDL, enabling the instructor to choose the language being used by the students.
9789353062019
621.395 MAN-D